Process for compressing and expanding structurally associated multiple-data sequences, and arrangements for implementing the process

ABSTRACT

A process and data processing system are disclosed for compressing and expanding structurally associated multiple data sequences. The process is particular to data sets in which an analysis is made of the structure in order to identify a characteristic common to a predetermined number of successive data elements of a data sequence. In place of data elements, a code is used which is again decoded during expansion. The common characteristic is obtained by analyzing data elements which have the same order number in a number of data sequences. During expansion, the data elements obtained by decoding the code are ordered in data series on the basis of the order number of these data elements. The data processing system for performing the processes includes a storage matrix (26) and an index storage (28) having line addresses of the storage matrix (26) in an assorted line sequence.

DESCRIPTION Technical Field

The invention relates to a process for compressing and expandingstructurally associated multiple data sequences, particularly data sets(records) in which data sequences to be compressed are stored inparallel in a storage matrix on the basis of their structuralassociation, performed for obtaining a characteristic connecting anumber of data elements of the data sequences for multiple datasequences as structural analysis of data elements of conforming ordinalnumbers, a code is used instead of these data elements and, duringexpansion, the data elements obtained by decoding the code are arrangedin data sequences on the basis of the corresponding data element ordinalnumber. The invention relates further to data processing systems forimplementing the process.

BACKGROUND ART

Data sequences are often redundant to a high extent, i.e. they contain abasically higher number of data elements or signs than are necessary forrepresenting the information they contain at the time. An example forthis is the regularly constructed data sets (records) for filespertaining to the economy and to the administration. A further exampleof this is the transmission of TV pictures in which the subsequentlytaken and then as data sequences stored or transmitted partial images,relative to individual areas of a scene, are identical, since they werenot exposed to any change relative to their position, light intensity orcolor of picture points (elements). This is the case for the majority ofpicture points without changing the scene. In order to be able to carryout the transmission of data sequences economically, it is necessary tocompress them and to expand them again at the end of the transmissionpath (route).

Processes are already known in which the compression of data sequencesis made by means of a coding of variable length. The coding diagram ofthis type effects that the bit strings of a fixed predetermined lengthare coded in bit strings of variable length, and bit strings of theoften occurring code words are represented shorter than code words of afixed predetermined length. This conversion of code words of a fixedlength into code words of variable length is known as Huffman-coding. Incase of a meaningful allocation of code words of variable length withthe given data, a considerably slighter length of such code words willthen result in comparison with the respective code words of apredetermined fixed length, though many code words of variable lengthare considerably longer than the corresponding code words of a fixedlength.

Furthermore, processes for compressing and expanding data sequences areknown in which a structural analysis is applied, in order to recognizein a predetermined number of data elements of data sequences acharacteristic that connects them. Such a characteristic can be, forexample, in a repeated occurrence of the same sign or can be given alsoin an increasing numerical character string of the type 1, 2 . . . . Thegiven number of data elements is converted then into a code. Such a codein a string of signs equal to n should contain at least a separatingsign, the respective sign and the number of its occurrence, in order tobe able to produce again the original string during expansion.

Further known is a process for compressing and expanding data sequencesin which two logically associated data sequences are interlinked by anEXCLUSIVE-OR before the compression proper of the usual type. Thislogical interlinkage (combination) effects that zeros are produced onthe points on which equal signs are present. Since the data sequencesare presumably logically associated by EXCLUSIVE-OR association, a datasequence is produced which often contains zeroes as data elements. Thedata sequence strongly interspersed with zeroes is then compressed inthe usual manner.

The structural association, especially the logic association of at leasttwo data sequences for the purpose of compressing, is used in thisprocess in order to improve the result of compressing. However, even inthis process, the result of compressing is still strongly redundant.Besides, a high technical circuitry expenditure is necessary for therealization of this process, since universal computers of highefficiency are required.

The same is true for a process of the initially mentioned type that isknown from the article "Data Compaction for Improved TransmissionEfficiency" by Dirk R. Klose in IEEE National TelecommunicationsConference, of Nov. 26 to 28, 1973, pp. 35C-1 to 35C-6. In this process,several data sequences of a predetermined length, forming together adata set, are arranged line by line in a matrix and compressed by codingcolumn by column into less redundant code sequences, so that theirstructural association is set in the direction of the columns andevaluated. Although it is possible to improve the result of compressionin this manner, the expenditure of the technical circuitry,nevertheless, remains high, especially when considering the matrix-likedata sequences arranged column by column.

SUMMARY OF THE INVENTION

Therefore, it is the task of the invention to act upon the datasequences by compressing and expanding several structurally associateddata sequences, especially data sets, in a manner so clearly improved incomparison with the heretofore applied processes that it can be realizedwith a considerably smaller expenditure for technical circuitry than wasnecessary heretofore.

This task is solved according to the invention, starting with a processof the initially mentioned type, so that, before the structuralanalysis, the stored data sequences are examined relative to theirlength, formed with data sequences of data sequence groups of equallength, and the data sequence groups are arranged according to anincreasing or decreasing length.

By the particular procedural step, executed according to the inventionbefore the structural analysis, it will be possible to consider in thestructural analysis to be executed step by step in compressing the dataelements only that part of the actual matrix column in which informationis available due to the foreseen order of the data sequence groups.Thereby it is possible to considerably reduce the expenditure for thetime of processing and thus of the techniques of circuitry. The resultof compressing will be simultaneously improved, since the ordering ofthe data sequence groups according to their length prior to execution ofthe structural analysis enables a comprehensive view of adjacent matrixcolumns of equal or of almost equal length, whereby matrix columns of acode sign, characterizing such a group, are saved. It has beendemonstrated that in an order of the data groups of this type even othercommon features of adjacent matrix columns are easier to be evaluatedand can lead to a shortening of the code words in the outcome of thecompression.

When organized data sequences of equally effective length and of equalcharacteristics are organized according to increasing or decreasingstorage matrix line number, in order to maintain as far as possible thestructural association of the data sequences read into the storagematrix line by line, the result of compressing can be thereby furthered.

In this process, it is possible to characterize advantageously theeffective data sequence length, at least one data sequencecharacteristic and the storage matrix line number by an attribute fieldthat completes each data sequence. It is then possible to have easyaccess to the order criteria.

In a further realization of the process according to the invention, theindividual data sequences are serially precompressed in order to use thestructural association given by considering serially the data elementsof the individual data sequences. If possible, the structural referencepoints for the column by column compression is not to be destroyed bythis process. This is obtained so that the compressed strings arereplaced in the data sequence by fill characters which are notconsidered during the compressing column by column proper. The structureof the individual data sequences remains thus maintained.

As one possibility of the serial precompression, the at the time lastdata element of at least one data sequence, as well as eventually thenumber of such data element and their repetition factor is taken overinto the attribute field. Furthermore, for shortening, the last dataelement, as well as its precursors, identical in the data sequence withthe former, are eliminated. This type of serial precompression proves tobe particularly advantageous, since the last data elements of a datasequence are often identical. Let us consider here, for example, emptycharacters, called blanks, at the end of the data sequences.

In case that the type of data sequence is not explicitly indicated, ithas proven to be advantageous to take over into the attribute the lastand the before last data element of the uncurtailed data element as adata sequence characteristic and to eliminate it in the data sequence.This is based mainly on the understanding that structurally similar datasequences, as far as to their data elements at the end of the datasequence, are identical.

The result of compression can be further improved when within theframework of serial precompression of the data sequences at least thecharacter string of a data sequence, consisting of equal data elements,is eliminated and replaced by fill characters, and when this string iswritten in a descriptor field provided for each data sequence separatelyby an index, marking the beginning of the character string, by thelength of the character string and the first character sign. By thismeasure, it is possible to compress most effectively long characterstrings of identical data elements without destroying thereby thestructure of the individual data sets, since the eliminated characterstrings are replaced by fill characters which are not considered in thecolumn by column compressing process.

Since the jittering (flowlike arrangement) of blanks or zero characters,for example, effects negatively the compression result in the process ofcompressing column by column, at least the greatest jittering of suchinterference characters in the data sequences to be compressed isdetermined within the framework of the serial precompression. Theinterference characters are replaced by fill characters and theinterference character itself is inscribed (written upon) by a jitteringindex marking the beginning of the interference field, by the length offield and by the first interference character.

Since all measures described within the framework of serialprecompression, as well as the sorting of data sequences based onvarious criteria, are unequivocal processes, they can be cancelledwithin the framework of expansion.

In a further design of the process according to the invention, at anytime at least one column descriptor field is foreseen for each dataelement column that is at least partly written in the data elementcolumn. According to a further development of the invention it istherefore possible, for example, to eliminate the data element columns,consisting of identical characters (signs), to replace them by fillcharacters of the actually replaced characters and to inscribe them inthe respective descriptor fields by an indication of the actuallyreplaced character. By inserting the fill character instead of theeliminated data column, the structure of the individual data sequenceremains maintained, since the field characters are bypassed in theprocess proper of compressing column by column.

According to another further development of the invention, at least thelongest character string of a data element column, consisting of equaldata elements, is eliminated and replaced by fill characters. Thischaracter string is further inscribed in the actual column descriptorfield by an index marking the beginning of the character string, by thelength of the character string and by the first character. By thisinscription of the character string, it is possible to reproduce itwithin the process of expansion and arrange it on the proper spot in thedata element column.

In another further development of the process according to theinvention, at least the longest character string of a data elementcolumn, consisting of identical data elements, is recoded into a shortercode word in comparison to the respective character string and isreplaced by this code word and the data element spots emptied by thisoperation are filled by fill characters.

In a further advantageous development of the process according to theinvention, two neighboring character strings of a data element columnare interchanged and are stored into the contact point of the characterstrings in the index, marking their original position and the lengths ofthe character strings in the descriptor field of the respective dataelement column.

In a further development of the process according to the invention, thedata elements of at least a part of a data element column in one forthis respective column specific, less redundant code, are recodedwhereby the result of compression can be further improved.

As a further measure for improving the result of compressing serves thelinkage of the individual data elements of the data element column bythe logical function with the truth table "A linked with B=W" in casethat A=B and "A linked with B=B", in case that A≠B on condition thatB≠W, where W is any selected repetition character, for example the zerocharacter. The application of this logical function for the dataelements of a data element column serves for the homogenization of thesedata elements. In case of a comparison of the data element B with thedata element A where the equality of B and A is determined, the dataelement B is replaced by the repetition character W. On the other hand,in a comparison of the data element B with the data element A where theinequality of B and A is determined, the data element B remainsunchanged. When this logical function is subsequently applied for thedata elements, for example in the data element column from below upward,it will be possible, for the sake of a one to one correspondence of thelogical function which is valid for the condition that B≠W, to restoreduring expansion the data element column with the original dataelements. After application of this logical function of the dataelements of all data element columns, the linkage results of two datasequences can again be always serially compressed.

In a further design of the process according to the invention, each dataelement of a data element column is recoded into a valuation orindicator code word, in case that the indicator code words of theindividual data elements are added bitwise to the data element column,adjacent indicator code words bitwise EXCLUSIVE-OR are linked, thelinkage results are also added and both additional results are evaluatedfor the classification of the data structure. In this case, theindividual bit positions of the valuation or indicator code words havelogical power over the type of the actual data element. It is thuspossible that, for example, a 1 in the fifth bit position of a valuationor indicator code word signifies that the first half character of therespective data elements is 0. By the bitwise addition of the indicatorcode word of the individual element of a data element column the logicis obtained stating how many data elements are available in the dateelement column which have their first half character 0. By the bitwiseEXCLUSIVE-OR linkage of adjacent indicator code words and by theaddition of the results of the linkage, a logic is obtained relative tothe frequency of the type of the individual data elements, whether theyare especially suitable for evaluating the classification of the datastructure.

Since the probability of a half characterwise confirmity, or at least acommon characteristic of the half characters of half elements of a dataelement column, is greater than in a complete data element, the resultof compressing can be improved when each data element column isconverted half characterwise into a kind of code word determined by theresult of the classification.

This is done in a simple manner so that the result of the classificationis expressed by m-bits which are formed from the m-bit classificationresult, together with an n-bit half character, comprising an (m+n) foraddressing a code memory containing the code words, and the addressedcode words are read out one after another from the code memory. By thisoperation, a storage range of the code storage is selected, containingthe part of the address of a higher value, comprising suitable codewords for the occurring half characters for the respective, by thehigher result of classification expressed data structure of the dataelement column.

In a further development of the process, both code words, read out atany time as the last ones from the code storage, are examined as totheir confirmity after each reading cycle of the code storage. Thismakes it possible to sum up and thus to compress in this way subsequentequal code words in a further step of the process.

This takes place in a further development of the invention so that thenumber of the directly subsequent reading cycles of the code storage arecounted, after which both code words, read out as last from the codestorage, always correspond. The result of counting indicates then howoften the type of the last from the code word read out from the codestorage has subsequently occurred.

A further development of the process according to the invention ischaracterized in that the counting result is interlinked in dependenceon the type of the code words so that the interlinked result of countingis discernible from the respective code words. This interlinkage servesfor a safe differentiation of the counting result from the code wordsoccurring in the code storage.

In a further development of the process according to the invention, thehalf characters, occurring preponderantly in a data element column, arerepresented only once, and each one of the remaining half characters, aswell as one index indicating the actual position of this remaining halfcharacter, are separately represented in the code of compression. Thistype of compression is especially suitable for widely homogenous dataelement columns interspersed by a few interfering characters only.

A data processing system for realizing the process is built according toa further development of the idea of the invention so that a storagematrix is provided on its address inputs with a first switchover deviceby which, in dependence on a first switchover signal, the line andcolumn addresses of the data element storage positions areinterchangeable. By this interchangeability of line and column addressesonly will it be possible to make the storage matrix readable linewise aswell as columnwise, and rewritable without the need of expensiverandomizing (conversion) of addresses requiring high computer power.Since the addressing of a storage matrix of order sets of conventionaldata processing systems is provided only linewise, the address of thesubsequent data element in the data element column had to be computedheretofore in a column by column processing, before the desired countingoperation could have been executed.

Furthermore, when an index storage is provided with its number of linescorresponding to those of the storage matrix, and having the lineaddresses of the storage matrix in an assorted sequence, it is possibleto have an assorted access to the data element storage positions of adata element column of the storage matrix in accordance with thesequence of lines of the line addresses in the index storage without theneed of a preceding expensive reassortment of the data element lines ofthe storage matrix. The actuation of the line address inputs of thestorage matrix by the output signals of the index storage isadvantageously done by a second switchover device controlled by a secondswitchover signal.

In a further development, an attribute and descriptor storage isforeseen with a third switchover device on its address inputs by which,in dependence on the third switchover signal, the line and columnaddresses of the storage positions are exchangeable. A separateattribute and descriptor storage, beside the storage matrix for the dataelements proper, has the advantage that in further developments of theprocess according to the invention in which an assorting of the datasequences is made, these must be reassorted, not in their totality, butbasically the contents only of the lines of the attribute and thedescriptor storage dependent on the assorting criteria. Dependent on theattribute and descriptor storage, the executed reassortment is thenloaded into the index storage so that the storage matrix proper can beaddressed from them in an assorted way. In order to be able to addressline by line, as well as also column by column without having to spendcostly recounting of addresses, a third switchover device for exchangingthe line and column addresses is foreseen on the inputs of the attributeand descriptor storages.

A decoder produced, for example, by one or more address bits of highervalue of decoding the actual switchover signal, is advantageouslyprovided for getting the actual switchover signal from the storageaddress.

According to a further development of the invention, a commercialmultiplexer is foreseen as a switchover device.

The data processing system for realizing the process can be designedequally so that a reading storage, containing the indicator code words,is foreseen and is addressable by the data elements. A certain indicatoror evaluation code word can thus be simply assigned to each data elementtype.

In a further development, a counter system is connected with the dataoutput of the readout storage with a double number of individualcounters in comparison with the bit number of the indicator code wordsand they are series connected to the half of the individual EXCLUSIVE-ORmembers the inputs of which have at times a bit position leading fromthe indicator code words directly adjacent in the readout storage. Bysuch an indicator system, it can be determined how often the dataelements of a data element column conform with the bit position and howmany bit changes between adjacent data elements of a data element columnare to be entered into an individual bit position. For determining theexchanges in the individual bit positions, two registers areadvantageously foreseen between the data output of the readout storageand the inputs of the EXCLUSIVE-0R members, serving as intermediatestorage of the actually last and the directly before last indicator codewords read out from the readout storage. In case that contents of bothregisters correspond, it signifies that the actually last and thedirectly before last indicator code words read out from the readoutstorage are identical. On the outputs of the EXCLUSIVE-OR members of theindividual bit positions appears then always the value of 0. However,should the contents of both registers not correspond in their individualbit positions, this signifies that in these bit positions a change tookplace between the actual last and the directly before last indicatorcode words read out from the readout storage. The value of 1 appearsthen on the outputs of the EXCLUSIVE-OR members of these bit positions.

The data processing system can be designed also by having a fixed datastorage (read-only memory) as code storage that can be addressed fromthe data structure-classification result of the data column to becompressed and from the actual half character of the respective datacolumn, and the data structure-classification result of the highervalued address part forms the higher valued address part and the actualhalf character of the low value address part. By the result of the datastructure-classification, the storage range, relevant for the respectivedata structure of the code storage, is addressed in this manner,containing suitable code words for the half characters to be compressed.

A first and second register is connected in parallel to the code storagein a further development, so that the first register stores temporarilythe actually last read out code word and the second register stores thedirectly before last code word. It is thus possible to obtain simpleaccess to both code words read at any time from the code storage.

In a further development of the data processing system, a comparatorcircuit is advantageously foreseen, connected with the outputs of thefirst and of the second register, in order to determine by it the codewords read always as the last from the code storage. Furthermore, acounter is foreseen, controlled by the comparator circuit, by which thenumber of the directly subsequent identical code words, read from thecode storage, can be counted.

In order to be able to encode in a simple manner the count of thecounter in dependence on the type of the code words, a multiplexercircuit is advantageously provided.

The data processing system is designed for the above described logiclinkage of data elements so that an A-register and a B-register areforeseen, serving also as a result register so that the outputs of bothregisters are bitwise connected with the inputs of EXCLUSIVE-0R membersand that outputs of the EXCLUSIVE-OR members are connected with theinputs of a disjunctive linkage the outlet signal of which controls theresetting (restoring) input of the B-register. This circuit arrangementis characterized by its simple design.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention is nearer explained in the following with the help of anexample of a typical data file and on the basis of examples ofembodiments of a storage system, an indicator system, a half charactercompressing system, and a circuit arrangement for logical linkage ofdata elements in a data processing system.

These embodiments in accordance with the invention are described withrespect to the drawings in which:

FIG. 1 is a file consisting of 37 data sets;

FIG. 2 is a diagram of an exemplary principle controlling a storagematrix by an index storage,

FIG. 3 is a schematic illustration of a storage matrix with two dataelements arranged in a matrix line;

FIG. 4 is the storage matrix of FIG. 3 with two data elements arrangedin a matrix column;

FIG. 5 is a circuit plan of a storage system;

FIG. 6 is an addressing diagram of the storage system of FIG. 5;

FIG. 7 is an indicator system for classification of the data structureof a data element sequence;

FIG. 8 is a detailed section of a counter arrangement shown in FIG. 7 asa block diagram;

FIG. 9 is a half character compressing device; and

FIG. 10 is a circuit arrangement for logically interlinking dataelements.

DETAILED DESCRIPTION

FIG. 1 shows a typical file consisting of hexadecimally represented dataelements. The 37 data sets that it comprises are assorted according totheir length. By means of this data file, it will be shown that theindividual data elements, viewing the data sets column by column on thebasis of their structural association, have greater common featuresamong one another than if considered data set by data set or line byline.

Let further mention that a compression of identical characters forexample, is meaningful only when these occur subsequently at least fourtimes, since the compression code must contain a sequence of compressingcharacters indicating separating characters, the compressed characterand the number of its occurrence.

Viewing, for example, in FIG. 1 the second data line, it is recognizablethat the data element F0 occurs successively as a single data element,on the one hand, four times and, on the other hand, five times.Therefore, by compressing identical characters, three data elementscould be saved in this data line, since basically the four and the fivedata element string can always be represented by three characters in theprocess of compression. On the other hand, considering, for example, thesecond data column of this data file, it can be seen that the dataelement 1C occurs successively twenty times and the data element 1Beight times. In the columnwise data-elementwise compression of identicalcharacters, it is possible to save twenty-two (=20+8-2×3) data elements.Finding further data lines and data columns, and comparing theircompression result, it will be seen that a columnwise data elementwisecompression comparison to a linewise data elementwise compression leads,as a rule, clearly to a better result. When the columnwise compressionof the data elements is realized even half characterwise, thecompression result will further improve. Viewing again the second datacolumn, it is observed that the half character or half byte "1" occurssuccessively altogether thirty-six times. A half character occurringsuccessively with such a frequency, can be compressed with the highestefficacy.

Since the data sets of a file are assorted as a rule not according totheir length, and since it is appropriate for the columnwise compressionof the data elements, when the individual data sets are arranged inorder to avoid gaps of data elements with a degressive length from abovedownward in the storage matrix, it is necessary to rearrange the datasets containing data lines of the storage matrix or, in order to saveprocessing time, to address the storage matrix in an assorted way. Asshown in FIG. 2, this is possible by a line addressing by means of anindex storage 20. The line addresses, contained in the index storage 20of the storage matrix 22, holding the individual data elements, mustbasically be reassorted so that the line 0 of the index storage 20contains the address of the line of the storage matrix 22 that holds thegreatest numbers of data elements. The line 1 of the index storage 20must then contain the address of the line of the storage matrix 22 thatholds the second greatest number of data elements, etc. After havingsuccessively selected the index storage 20 and read from line 0 to line9, the line addresses of the storage matrix 22, contained in the indexstorage 20, the individual lines containing the data sets of the storagematrix 22, will be addressed assorted on dependence of the length of thedata sets.

FIG. 3 shows a storage matrix consisting of ten lines and sixteencolumns addressable with decimal addresses, and also its addressingdiagram. As seen in FIG. 3, the data element X is addressed by theaddress 509. The address part of higher value, i.e. the digit 5 is theline address, and the low value address part, i.e. the digit sequence 09is the column address. The digit 0, placed in front of the address 509,serves merely as a reversing switch and is not needed for the addressingproper of the data element X. Since, for the usual successive storageaddressing, the address of the following data element ensues basicallyby increasing the digit of the storage address by 1, the data element Ythat has the same line address as the data element X and the columnaddress of which, in comparison to the column address of the dataelement X is addressed as the following data element, has a value thatis higher by 1. The fact that in the successive storage addressing thedata element Y is addressed in the same line after the data element Xand not the data element Z in the same column, is explained so thatusually the line address forms the higher value address part and thecolumn address the low value address part that is then counted higher.

If, on the other hand, in a successive storage addressing, after thedata element X is the next data element Z, i.e. as first addressed isthe data element of a column, it becomes necessary that the storagematrix be addressed with an address in which, as shown in FIG. 4, theline address is substituted by the column address. When the columnaddress 09 forms the address part of higher value and the line address 5the address part of a lower value, then the line address is countedhigher. With the digit of the address raised by 1, the line address of avalue 5 is raised higher to the value 6, with the column addressremaining at the same value. Thus, after the data element X, the dataelement Z is addressed as the next character. This substitution of theline address by the column address can also be executed by means of theso called reversing switch. In case that the reversing switch, as shownin FIG. 3, is of the value of 0, for example, this signifies that theline address does not have to be substituted by the column address, withthe result that with a successive storage addressing, the storage matrixwill be addressed line by line. On the other hand, in case that thereversing switch is of the value 1, as shown in FIG. 4, this signifiesthat the line address must be substituted by the column address foraddressing the storage address, from which follows that by successiveaddressing of the storage matrix, it will be addressed column by column.

FIG. 5 illustrates a block diagram of a storage system that isespecially suitable for executing of the process according to theinvention. This storage system contains basically a matrix storage 24, astorage matrix 6, an index storage 28, connected with a data buffer 30,a program storage 32, a 1 among 16 decoder 34, a first multiplexer 36, asecond multiplexer 38 and a third multiplexer 40. In order to understandthe design and the way of operation of this storage system, it is firstnecessary to indicate the outlay of this storage system. This will beexplained in the following, according to FIG. 6 in connection with FIG.5.

The range of addressing 00000 to 0FFFF is assigned to the 64K byteprogram storage 32. The address range 10000 to 100FF serves foraddressing the 256 bytes of the index storage 28. The addressing 10100to 1FFFF are not used in this storage system. The address range 200000to 2FFFF serves for addressing the 64K bytes comprising matrix storage24 line by line. The address range 30000 to 3FFFF serves for addressingmatrix storage 24 column by column. Finally, the storage range 40000 toFFFFF is assigned to storage matrix 26. The 256K bytes of this storagematrix 26 are to be addressed line by line when in the address range40000 to 7FFFF. They are further addressable column by column in theaddress range 80000 to BFFFF. In the address range C0000 to FFFFF, theyare additionally indexed column by column, i.e. they are addressablyassorted. Since in this storage system the matrix storage 24 and thestorage matrix 26 are repeatedly differently addressable, the virtualstorage range of the storage system is clearly larger than the bodilyavailable storage range. While the latter is illustrated in FIG. 6 asnot hatched, the virtual storage range is shown simply hatched. Thecrosswise hatched storage range is not used for this storage system.

Therefore, the storage system shown in FIG. 5 has, including thereversing switch for the various types of addressing, an address rangeof 1 Megabyte. 20 bits are necessary for the selection of the address,i.e. 20 address lines A0 to A19, in order to be able to address with awriting or reading access a byte as the smallest storage unit. The datalines are so called bidirectional lines, i.e. the information comes inreading operations from the storage system. In writing operations, onthe other hand, it is led by these lines (conduits) into the storagesystem. The signal WR controls the storage operations READING andWRITING. While this signal is logically 0 when the operation WRITING isexecuted, the signals are logically 1 when they are active. Storagemodules (building blocks) can be used for the design of this storagesystem.

The function of this storage system is more specifically explained inthe following. The selection of the program storage 32 is made when theaddresses A16 to A19 are logic 0. That is determined by the 1 of 16decoder 34. Its outputs are logic 1 in inactive state, while in activestate they are logic 0. When thus the address bits A16 to A19 which areadjacent at the input of the decoder are logic 0, then at the output "0"of the decoder 34 appears the signal logic 0 that controls the selectinput 44 of the program storage 32. Since the select input 44 is anegative input, the program storage 32 is selected when the signal islogic 0. As already mentioned above, the same is valid for the inputWRITE 46, i.e. when the signal WR is logic 0, writing will take place inthis storage range. On the other hand, when this signal is logic 1, itwill be read from this storage range and the information signals areconnected to the data bus. Since the storage matrix 26 (address range40000 to FFFFF) with the address bits A18 and A19 can be unequivocallyselected, the outputs 4 to 15 are not used in the decoder 34.

The index storage 28 is selected in the address range 10000 to 100FF inreading operation, as well as in writing operation, and also for theindexed addressing of the storage matrix 26 within the address rangeC0000 to FFFFF in reading operations only. In the last address range, awrite-in into the index storage 28 is prevented by the logic linkage ofthe signal WR with the address signals A18 and A19 by an AND member 48,an inverter 50 and a NAND member 52. For the selection of the indexstorage 28, the signal of the outlet "1" of the decoder 34 is ledthrough an inverter 54 into a NOR member 56, the output signal of whichcontrols the select input 58 of the index storage 28. The selection ofthis index storage 28 takes place for the address range C0000 to FFFFFnot by means of the decoder 34 but directly by means of the addresssignals A18 and A19.

Both these signals are interlinked by means of the AND member 48, theoutput 60 of which is connected with the NOR member 56. The indexstorage 28 must have a very short access time, since the data of thisstorage become necessary within a storage cycle for the address of thestorage matrix 26.

Since the index storage 28 is written upon only in the address range10000 to 100FF and not in the address range C0000 to FFFFF, the databuffer 30 is utilized and allows the flow of information from the dataline 42 to the index storage 28 in the address range 10000 to 100FF. Thecontrol of this data buffer 30 is provided by the signal occurring onthe output 1 of the decoder 34, as well as by the signal WR.

The storage matrix 26 consists of 256 lines per 1024 bytes, whichresults in a storage range of 256K bytes. For addressing the 256 lines,a line address of 8 bit length, and for addressing the 1024 columns, acolumn address of 10 bit length are necessary. That results for thisstorage matrix 26 in an 18 bit address. Since this storage matrix 26 forthe address range of 40000 to 7FFFF is addressed line by line, and forthe address range 80000 to FFFFF is addressed column by column andindexed addressed column by column, the address signal of the highestvalue A19 for controlling the first multiplexer 36 can be applied. Whenthe address signal A19 is 0, the 0 inputs of the multiplexer are used.No substitution of line and column addresses takes place in this case,so that the storage range is addressed line by line. On the other hand,when the address signal A19 is 1, the inputs of the multiplexer 36 areconnected to the storage matrix 26 in a manner resulting in asubstitution of line and column addresses. The address signals A8 to A17are then led to the column address and the signals X0 to X7 to the lineaddress. The selection of these address signals for storage matrix 26takes place when at least one of both address signals A18 and A19 isactive. They are therefore disjunctively interlinked by an OR-member 60,the output signal of which controls the select-input 62 of the storagematrix 26.

The signals X0 to X7 stem from the second multiplexer 38. With this itis possible to obtain a switchover from the address signals A0 to A7 tothe output signals 10 to 17 of the index storage 28. The switchover isnecessary when the storage matrix 26 has to be index addressed bycolumn. Should this result for the storage range C0000 to FFFFF, theswitchover must follow when both peak value address signals A19 and A18are simultaneously 1, i.e. when the signal SE is 1 at the output of theAND-member 48.

Since the storage range 20000 to 3FFFF is assigned to the matrix storage24, the selection of this matrix storage 24 ensues with the signals ofthe S2 and S3 of the decoder 34. These signals are inverted by theinverters 4 and 66, respectively, and then linked by a NOR member 8, theoutput of which is connected with the select input 72 of the matrixstorage 24. This encompasses a storage range of 256×256 bytes=64K bytes.Therefore, for its addressing, only a 16 bit address is necessary,consisting of an 8 bit line (row) and an 8 bit column address. This 16bit address is led to the matrix storage 24 from the third multiplexer40. The control of this multiplexer 40 ensues by the signal S2 from thedecoder 34. When this signal is logic 0, the 0 inputs of the multiplexer40 are used for forming the 16 bit address of the matrix storage 24.These 0 inputs are actuated by the address bits A0 to A15 in theascending normal address sequence. In the 1 inputs of the multiplexer40, the column and line address bits of the matrix storage 24 arearranged interchanged. In this case, the address A8 to A15 is the columnaddress, while the address A0 to A7 represents the line address. Byswitching over the address by the multiplexer 40, it is possible toaddress the matrix storage 24 line by line, as well as column by column.The matrix storage 24 serves in this execution of the above describedprocess as an attribute and descriptor storage.

FIG. 7 shows an indicator system for the classification of the datastructure of a line of data elements. It consists of an interfacecontrol circuit 74 that controls the bidirectional data traffic, a readonly (ROM) storage 76 to which a register E and a register F areconnected in parallel. A counter arrangement 78 is connected with theoutputs of these registers, comprising (8×2) 8 bit individual counters.A 1 of 16 select circuit 82 is controlled by a further counter 80 havinga 4 bit output. A control unit 84 is provided for controlling thesecomponents.

Since the design of this indicator system has been described above, theway in which it functions will be explained in the following, based onFIG. 7 in connection with FIG. 8. First, the data elements, for exampleof a data element column, are led to the interface control circuit 74.The control unit 84 is activated by the signal RD and emits a takeoverof the data elements. These latter serve for addressing the singlecolumn read only storage 76 consisting of 256 lines containing theindicator code words. At the beginning of the first cycle for receivingthe first indicator code word into the registers E and F, all counterswill be reset by the single NORM signal. During a cycle, an indicatorcode word, corresponding to a data element, is then taken over into theregister E by the clock T1. With the clock T3 that follows with adistance of time after the clock T1, the same indicator code word istaken over into the register F. In FIG. 8, the one 2×8 bit-countercombination of the counter arrangement 78 of FIG. 7 is shown in detail.For each bit of the registers E and F, there are two bit countersforeseen. In this arrangement, the counter 86 counts, for example, howoften the bit 0 of the register E is logic 1, and the counter 88 showsthe switchover from 0 to 1 or in reverse. This is realized with thecounter 86 so that an AND member 90 is series connected with a counterinput having on its inputs the signal E0 of the register E and the clockT2. The clock T2 is placed, at the time, between clock T1 and clock T3.In case the bit EO of the register E has the value 1, the counter 86 israised by 1 when clock T2 is a logic 1.

The switching from 0 to 1 or in reverse, for example in the bit position0, is determined by the signals E0 and F0 of the registers E and F.These signals are led to an EXCLUSIVE-OR member 94, the output of whichis connected with the input 96 of an AND member 98. The output signal ofthis AND member 98 controls the counter 88. When the signals E0 and F0do not correspond, the output signal of the EXCLUSIVE-OR member 94 islogic 1. In this case, the counter is raised by 1 when the clock pulseT2A occurs. The clock pulse T2A occurs between the time of clock T1 andthe time of clock T2. Since an indicator code word that is present onthe output of the read only (scanning) storage 76 is taken over duringthe clock pulse T1 into the register E and taken over into the registerF when clock pulse T3 occurs, at the time of clock pulse T2A theindicator code word that is available at the output of the read onlystorage 76 is stored only in the register E. The register F then stillmaintains that indicator code word which has been read during thedirectly precedent cycle from the read only storage 76. It can thus bedetermined, with the help of the counter 88, how often adjacentindicator code words of a data sequence differ at the bit position 0. Inthis counter arrangement, it is important that the clock pulse T2A issuppressed in the first clock cycle, since the number of bit changeswill otherwise be incorrectly counted.

After the interface control circuit 74 has taken over all data elementsof a data element line (row), the signals SELECTION 0 to SELECTION 16will be successively produced by the 1 of 16 selection circuit 82, wherethe signals SELECTION 0 and SELECTION 1 control both line drivers 92 and100. First, the count of the counter 86 is passed by the line driver 92and by the interface position control circuit 74 to the data bus. Aftereach output of the counter count, the counter 80 will be counted higherby 1 by a signal C produced by the control unit 84. The counter count ofthe counter 80, raised by 1, serves for selecting the followingindividual counter of the counter arrangement 78.

Since there are two individual counters available for each bit of theindicator code words as shown in FIG. 8, it is possible to determine foreach position of the indicator code words of a data sequence how oftenthe respective bit position is 1 and how often an exchange from 0 to 1or in the opposite direction takes place. There are thus, altogether,8×2=16 8-bit individual counters foreseen. The evaluation of the counterresults can be made by means of software, for example.

FIG. 9 shows the block diagram of a half character compressing devicefor data words of 8 bit length. It encompasses an interface circuit 102by which the data transfer and the data control are performed. Connectedin parallel with it are a MODUS register 104, on the one side, and amultiplexer 106 with a subsequent character register 108, on the otherside. The outputs of the character register 108 are connected with theinputs of recognition circuit 110 for a fill character, for exampleX'F'. They are further connected to the low value portion of the addressinputs of a read only storage memory 112, called in abbreviation a"ROM." The address inputs of higher value of this ROM 112 are connectedwith the four low value outputs of the MODUS register 104. The ROM 112altogether is addressable with an 8 bit address and holds thus maximally256 lines (rows). For each address there are 14 bits stored in the ROM112. While maximally 9 bits are foreseen for representing the characteritself, the number of the valid left justified character bits is codedin the further 4 bits. A bit is also foreseen in case of an error. Itsets then the bit M6 of the MODUS register 104. The remaining outputs ofROM 112, having 13 bits, are connected with a G register 114 and with anH register 116. The G register 114 contains the data present just at theoutput of the ROM 114, and the H register 116 contains the data whichwas read out as the last ones from the ROM 112. The outputs of bothregisters 114 and 116 are connected with a 13 bit comparator 118.

Furthermore, a counter 120 is foreseen that will be counted higher independence on the result of the comparison of the comparator 118. Theoutputs of this counter 120 are connected, just as the outputs of the Hregister 116, with the inputs of a 13 bit multiplexer circuit 122. Tothis, connected in parallel, is a 9 bit shift register 124, as well as ashift counter 126. The serial output of the shift register 124 isconnected with an input of a buffer storage (memory) 127. A charactercounter 128 is further foreseen and is counted higher by 1 when takingover at any time 8 bits from the shift register 124 into the bufferregister 127. The functionally suitable cooperation of theabove-mentioned components of the half character compression device iscontrolled by a microprocessor 130.

The way of functioning of this half character compression system is morespecifically explained in the following. When a sequence of 8 bit datawords, for example a data element column of a storage matrix, has to becompressed, first of all, the classification result produced for therespective data column is taken over from the above-described indicatorsystem by the interface circuit 102 and written into the MODUS register104. This MODUS register 104 has 8 bits, from which 6 bits are fed bythe signals D0 to D5. The remaining bits are error indications. The bitsM0 to M3 serve here for storing the classification result obtained fromthe indicator system by which the kind of compression is determined. Thebit M4 indicates whether a fill character, in this case the halfcharacter X'F', has to be suppressed. The bit M5 serves for switchingover the data selection, i.e. by bit M5 it will be determined whether inthe data words to be consecutively taken over, the bits D0 to D3 orD4-D7 are to be pulled out as half characters which are to becompressed. It indicates when data could not be correctly compressed.The bit M7 remains free.

After loading the MODUS register 104, the data words of the data elementcolumn to be compressed are successively taken over by the interfacecircuit 102 and are led to the multiplexer 106. From this, depending onthe MODUS register bit M5, either the data bits D0 to D3 or the databits D4 to D7 are selected and led to the character register 108.Consecutively, the data bits taken over from the character register 108by the recognition circuit 110 for the fill character, in this case forthe half character X'F', are checked out. In dependence on the MODUSregister bit M4, the taken over 4 bit half character is then suppressedwhen it is identical to the half character X'F'. The ROM 112 is thentaken over by the bits M0 to M3 of the MODUS register 104 as an addressportion of higher value, and addressed as a low value address portion bythe character register 108. The 4 bits M0 to M3 indicate here how theactual half character has to be converted. Since, on the basis of the 4bit length of the half characters, only maximally 16 different halfcharacters can occur, 16 lines in ROM 112 are foreseen for each type ofcompression determined by the 4 bits of higher value of the ROM addressin which are contained the compression code words of the half charactersfor the respective type of compression. Beside the maximal 9 bits forrepresenting the half characters, in ROM 112 there are always 4 furtherbits foreseen in each line reproducing the number of the valid leftjustified code word bits. As already mentioned above, the 14th bit isforeseen for the case of an error and sets the MODUS register bit M6.

The G register 114 and the H register 116 are loaded from ROM 112 sothat the G-register 114 always contains the last read out value of theROM 112 and the H register 116 contains the directly before last readvalue. Both registers 114 and 116 are compared by the comparator 118after reception of each code word. The counter 120 counts how often bothregisters 114 and 116 are directly identical successively after havingtaken over a new code word. With the help of the multiplexer circuit122, either the content of the H register 116 or the count of thecounter 120 is put out (emitted) on the shift register 124 and on theshift counter 126. The microprocessor 130 controls here the multiplexercircuit 122. When the registers 114 and 116 do not coincide severaltimes, the content of the H-register 116 is always led to the shiftregister 124 and to the shift counter 126. The shift register 124receives here the maximal 9 bits of the compression code word, and theshift counter 126 receives the valid left justified code word bits ofthe shift register 124.

On the other hand, when the registers 114 and 116, for example, coinciden times successively, first the contents of the H register 116 are putout with the help of the multiplexer circuit 122 on the shift register124 and on the shift counter 126. The counting result of the counter 120of the multiplexer circuit 122, controlled by the microprocessor 130, isled to the multiplexer circuit 122 and recoded by the latter independence on the fixed type of compression, determined by theclassification result of the indicator system. The shift counter 126contains, even in this case, the number of the valid left justified bitsof the shift register 124. These bits, controlled by the shift counter126, are put out on the buffer storage 127. The bits, taken over fromthe former, are counted, and the character counter 128 is raised alwaysby 1 whenever 8 bits are taken over. After compression of all dataelements, of the data element column, the buffer storage 127 will befilled by zeros for as long as the stored bit number will amount to aneven number multiple of 8 bits. The contents of the buffer storage 127,which contains now the data elements of the data element columns ascompression code words, will then be led to the interface storage 102and then put out (emitted).

The selection signals of the entire compressor, consisting of two halfcharacter compression systems, are designed so that both half charactercompressing systems can work 4 bitwise in parallel. However, the modusadjustment and readout of the results can follow separately.

FIG. 10 shows a circuit arrangement for logic linkage of data elementsaccording to the following truth (Boolean operation) table:

    A×B=0 when A=B

    A×B=B when A≠B

on condition that B≠0, with 0 as a repetition character.

This circuit arrangement consists of an A register 132, a B register134, an 8 EXCLUSIVE-OR member 136 by which the A register 132 and the Bregister 134 are interlinked bit by bit, an OR member 138 that linksdisjunctively the outputs of the 8 EXCLUSIVE-OR members 136, and of aninverter 140 by which the output signal of the OR member 138 is led toan input of the AND member 142. The second input of the AND member 142is actuated by the clock T2. The B register 134 can be reset by theoutput signal RES B of the AND member 142.

When 8 bit data elements A and B are logically interlinked according tothe above function, they will be loaded with the clock T1 into the Aregister 132 and into the B register 134. By the bit by bit EXCLUSIVE-0Rlinkage of the contents of the two registers 132 and 134, a signal logic0 is obtained on the outputs of those EXCLUSIVE-OR members 136 for whichthe inputs are identical. When the contents of both registers 132 and134 are identical in all bit positions, the signal logic 0 appears onall outputs of the EXCLUSIVE-OR members 136, so that on the output ofthe OR member 138 lies equally the signal logic 0 and consequently, onthe output of the inverter 140 is the signal logic 1. The AND-linkage ofthe logic 1 signal on the output of the inverter 140 with the clocksignal T2, effects by the AND member 142 the result that with the clocksignal T2 being a logic 1, the signal RES B will also be a logic 1. Thissignal resets the B register 134 so that it contains zeros on all bitpositions.

On the other hand, when the output signal of at least one of the 8EXCLUSIVE-OR members 136 is logic 1, which is the case when the contentsof both registers 132 and 134 do not coincide in at least one bitposition, the signal logic 1 then appears at the output of the OR member138. This signal, after inversion by the inverter 140, is led to the ANDmember 142. In this case, the signal level logic 0 remains maintained onthe output of the AND member 142 when the clock signal T2=1, with theconsequence that the B register 134 is not reset and keeps its content.

It should be noted that the various details of the processes and systemsdescribed herein as exemplary embodiments in accordance with theinvention are not meant to be exhaustive. It will be apparent to thoseskilled in the relevant arts that other modifications and variations ofthe above-described illustrative embodiments of the invention can beeffected without departing from the spirit and scope of the novelconcepts of the invention.

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:
 1. Process of compression and expansion of several structurally associated data sequences, including data sequences comprising data sets to be compressed, wherein the data sets to be compressed are stored in parallel in a storage matrix with regard to their structural association for obtaining a number of data elements of the data sequences of linking characteristic for several data sequences, the process comprising the steps of:compression of the data sequences by applying codes in substitution and representative of the data elements of coincident ordinal numbers; expansion of the data sequences by encoding the codes and obtaining the data elements, and arranging the data elements in data sequences with regard to the respective actual data element ordinal number; characterized in that the process further comprises the steps of: evaluation of the lengths of the data sequences, prior to performance of the structural analysis; formation of data sequence groups comprising data sequences of equal length, prior to performance of the structural analysis; and arrangement of the groups of data sequences in accordance with increasing or decreasing length of the sequences, prior to performance of the structural analysis.
 2. Process according to claim 1, characterized in that the data sequences of each data sequence group are evaluated as to identity of characteristics and are arranged in accordance with the evaluation.
 3. Process according to claim 2, characterized in that storage matrix-line numbers are determined for the arranged data sequences of equal effective length and identical characteristics, and the data sequences are arranged in accordance with increasing or decreasing storage matrix-line numbers.
 4. Process according to claim 1, characterized in that an attribute field is generated for each data sequence and completes the corresponding data sequence, with the attribute field containing at least the effective length of the data sequence, a data sequence characteristic and the storage matrix-line number of the corresponding data sequence.
 5. Process according to claim 1, characterized in that individual data sequences are serially precompressed.
 6. Process according to claim 4, characterized in that the last data element of at least one data sequence, as well as eventually the number of such data elements, representing a repetition factor, is taken over into the attribute field, and that this last data element, as well as the direct precursors coinciding with the last data element, are eliminated for shortening the data sequence.
 7. Process according to claim 6, characterized in that the last and the next to last data elements of the unshortened data sequence are taken over as data sequence characteristics into the attribute field and are eliminated in the data sequence.
 8. Process according to claim 5, characterized in that at least the longest of the equal data elements consisting of a character string of a data sequence is eliminated and replaced by a fill character, and the character string is inscribed into a descriptor field, provided separately for each data sequence by an index, marking the beginning of the character string by the length of the character string and by the replaced character.
 9. Process according to claim 5, characterized in that at least the greatest jittering of interfering characters are ascertained in data sequences to be compressed, fill characters, and the interfering character field is inscribed by a jittering index, marking the beginning of the interfering character by the field length and by the replaced interfering character.
 10. Process according to claim 1, characterized in that for each data element column always at least one column descriptor field is generated that inscribes, at least partly, the data element column.
 11. Process according to claim 10, characterized in that the data element columns consisting of identical characters are eliminated, replaced by fill characters and inscribed in the respective descriptor fields by indication of the actually replaced character.
 12. Process according to claim 11, characterized in that at least the longest character string of a data element column consisting of identical data elements is eliminated and replaced by fill characters, and the character string in the respective column descriptor is inscribed by an index marking the beginning of the character string, by the length of the character string and by the replaced character.
 13. Process according to claim 11, characterized in that at least the longest character string of a data element column is recorded in a code word that is shorter in comparison with the respective character string and is replaced by this code word, and the data element places which have been thereby set free are filled with fill characters.
 14. Process according to claim 10, characterized in that two adjacent character strings of a data element column are exchanged, and that an index marking the contact place of the character strings in their original position and lengths of the character strings in the descriptor field of the respective data element column are stored.
 15. Process according to claim 10, characterized in that the data elements of at least a portion of a data element column are recorded in a code that is less redundant.
 16. Process according to claim 10, characterized in that the data elements of a data element column are interlinked by the logical function with the truth table

    A×B=W, when A=B and

    A×B=B, when A≠B

on the condition that B≠W, where W is a repetition character.
 17. Process according to claim 1, characterized in that each data element of a data element column is coded into an evaluation or indicator code word, the indicator code words of the individual data elements are bit by bit added to a data element column, directly adjacent indicator code words are bit by bit EXCLUSIVE-OR interlinked, the linkage results are added, and both additional results are evaluated for the classification of the data structure.
 18. Process according to claim 17, characterized in that each data element column is half characterwise reset into code words determined by the result of classification.
 19. Process according to claim 18, characterized in that the classification result is expressed by m-bits, that from the bit classification result, together with as n-bit half character, an (m+n) bit address is formed for addressing a code storage containing the cord words, and that the addressed code words are successively read out from the code storage.
 20. Process according to claim 19, characterized in that the two code words last read out from the code storage at any given time are evaluated for equality after each reading cycle of the code storage.
 21. Process according to claim 20, characterized in that the number of the directly successive reading cycles of the code storage are counted, after which at any given time the two code words last read out from the code storage will coincide.
 22. Process according to claim 21, characterized in that the counter result is coded in dependence on the type of the code words so that the coded counter result is discernible from the respective code words.
 23. Process according to claim 18, characterized in that in a data element column preponderantly occurring half characters are represented once, and each one of the remaining half characters, as well as an index, indicating the actual position of this remaining character, is separately represented in the compression code.
 24. A data processing system for performing compression and expansion of several structurally associated data sequences, including data sequences comprising data sets to be compressed, the system comprising:a storage matrix for storing the data sets to be compressed in parallel with regard to their structural association so as to obtain a number of data elements of the data sequences of linking characteristic for several data sequences; means for compressing the data sequences, including means for applying codes in substitution and representative of the data elements of coincident ordinal numbers; means for expanding the data sequences by decoding the codes and obtaining the data elements, and arranging the data elements in data sequences with regard to their respective actual data element ordinal number; characterized in that the data processing system further comprises; means for evaluating the lengths of the data sequences prior to performance of the structural analysis; means for forming data sequence groups comprising data sequences of equal length, prior to performance of the structural analysis; means for arranging the groups of data sequences in accordance with increasing or decreasing length of the sequences, prior to performance of the structural analysis; address inputs connected to the storage matrix; and a first switchover device exchangeable in dependence on a first switchover signal, with the line and column addresses of the places of the data element storage.
 25. Data processing system according to claim 39, characterized in that the system further comprises an index storage having its number of lines equal to those of the storage matrix and which contains the line address of the storage matrix in an assorted line sequence.
 26. Data processing system according to claim 25, characterized in that the system further comprises a second switchover device by which the line address inputs of the storage matrix can be actuated in dependence on a second switchover signal with the outputs of the index storage.
 27. Data processing system according to claim 39, characterized in that the system further comprises an attribute and descriptor storage connected on its address inputs with a third switchover device by which, in dependence on a third switchover signal, the line and column addresses of storage places of the storage are exchangeable.
 28. Data processing system according to claim 39, characterized in that the system further comprises at least one decoder for obtaining the actual switchover signal from the storage address.
 29. Data processing system according to claim 39, characterized in that the actual switchover device is a multiplexer.
 30. Data processing system according to claim 39, characterized in that the system further comprises:means for coding each data element of a data element column into an evaluation or indicator code word; means for adding, bit by bit, to a data element column the indicator code words of the individual data elements; means for EXCLUSIVE-OR interlinking, bit by bit, directly adjacent indicator code words; means for adding the linkage results; means for evaluating both additional results for the classification of the data structure; and wherein the system comprises at least one indicator code word containing reading storage and addressable by the data elements.
 31. Data processing system according to claim 30, characterized in that the system further comprises a counter arrangement connected with a double number of individual counters in comparison with the bit number of indicator words with a data output of the reading storage and that half of the individual counters have an EXCLUSIVE-OR member series connected, to the inputs of which at any time a bit position of directly adjacent indicator words in the reading storage is admitted.
 32. Data processing system according to claim 31, characterized in that between the data output of the reading storage and the inputs of the EXCLUSIVE-OR members the system comprises two registers which serve for intermediate storage of an immediately prior indicator code word read out from the reading storage.
 33. Data processing system according to claim 39, characterized in that the system further comprises fixed data storage as code storage that is addressable by a data structure classification result of a data column to be compressed and by an actual half character of the respective data column, where the data structure classification forms an address portion of a higher value and the actual half character forms an address portion of a low value.
 34. Data processing system according to claim 33, characterized in that a first and a second register are connected in parallel to the code storage for intermediate storage, at any given time, of the immediately prior and next to immediately prior read code words.
 35. Data processing system according to claim 34, characterized in that a comparison circuit that controls a counter is connected with the outputs of the first and of the second register.
 36. Data processing system according to claim 24, characterized in that an A register and a B register are provided, serving also as result register, that the outputs of both registers are connected bit by bit with the inputs of the EXCLUSIVE-OR members, and that the outputs of the EXCLUSIVE-OR members are connected with the inputs of a disjunctive linkage member, the output signal of which controls the resetting input of the B register.
 37. Data processing system according to claim 35, characterized in that for coding of a counter count of the counter, depending on the kind of code words, a multiplexer circuit is provided, containing the code words to be coded. 